Design: A Simple Common-Source Amplifier

• Instructions: This activity is structured as a tutorial with an activity at the end. Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
• At the end of this activity, the student should be able to:

1. Design a simple common-source amplifier.

Activity 1: Transistor Intrinsic Gain

We can determine the intrinsic NMOS small-signal gain, $a_{0}=g_{m}\cdot r_{o}$, for a desired DC operating point, i.e for a given drain current, $I_{DC}$, and drain-to-source voltage, $V_{DS}$. This implies a certain gate-to-source voltage, $V_{GS}$. For square-law devices, we can easily calculate the required $V_{GS}$ that corresponds to $I_{DC}$ and $V_{DS}$. However, for deep submicron devices that do not follow the square law, we can either run simulations to determine this $V_{GS}$, or instead, we can let SPICE calculate $V_{GS}$ for us. As seen in Fig. 1, we can use negative feedback to obtain the appropriate $V_{GS}$.

Figure 1: The NMOS intrinsic gain simulation setup.

Figure 2: The NMOS intrinsic gain.

Using the circuit in Fig. 1, with $W=40\mathrm {\mu m}$, $L=0.15\mathrm {\mu m}$, $I_{D}=1\mathrm {mA}$, and the ideal amplifier gain, $A_{v}=1000$:

• Sweep $V_{DS}$ from 200mV to 1.8V, and plot $V_{GS}$ as a function of $V_{DS}$.
• From the $V_{GS}$ vs. $V_{DS}$ plot, derive the NMOS instrinsic gain, $a_{0}=\left({\frac {\partial V_{GS}}{\partial V_{DS}}}\right)^{-1}$, as a function of $V_{DS}$.
• Repeat for transistor lengths of $0.20\mathrm {\mu m}$, $0.25\mathrm {\mu m}$, $0.30\mathrm {\mu m}$, $0.35\mathrm {\mu m}$, and $0.40\mathrm {\mu m}$, and generate the graphs in Fig. 2.

You can use a voltage-controlled voltage source (VCVS) to model the ideal amplifier. Aside from obtaining the intrinsic gain at different lengths, we can use this circuit as a replica bias generator, to generate the DC input voltage of a common-source amplifier using the same transistor, as shown in Fig. 3.

Design: A Common-Source Amplifier

Now that we have obtained the transistor (1) large-signal characteristics, i.e. the transfer and output characteristics, (2) the small-signal parameters, $g_{m}$, $r_{o}$, $f_{T}$, and $a_{0}$, and (3) the figures of merit, $V^{*}=V_{ov}={\frac {2I_{D}}{g_{m}}}$ and $f_{T}\cdot {\frac {g_{m}}{I_{D}}}$, we can now put everything together and design a simple amplifier.

Part 1

You are tasked to design a simple common-source amplifier biased with an ideal current source, with the following specifications:

• Small-signal low-frequency voltage gain: $\left|A_{v}\right|=\left|{\frac {v_{out}}{v_{in}}}\right|>40$ for an output DC voltage of ${\frac {V_{DD}}{2}}=0.9\mathrm {V}$, and an output swing of at least $400\mathrm {mV}$ ($\pm 200\mathrm {mV}$ around $0.9\mathrm {V}$)
• Unity-gain frequency: $f_{u}=100\mathrm {MHz}$ for a load capacitance $C_{L}=5pF$
• $V^{*}=200\mathrm {mV}$

Figure 3: A simple NMOS common-source amplifier, where the output voltage, $v_{out}$, is the voltage across the load capacitor, $C_{L}$.

You are to submit:

• A short description of the design procedure you used to obtain $I_{D}$, $W$, and $L$.
• Any calculations you have done.
• A DC sweep of $v_{out}$ vs. $v_{in}$.
  • What is the maximum symmetric output voltage swing for $\left|A_{v}\right|>40$?
  • What is the corresponding input voltage swing?
• A plot of the magnitude response showing the low frequency gain, and the unity-gain frequency.
• Are these your expected results?

Part 2

You now wish to test the technology and design an amplifier has the highest unity-gain frequency, $f_{T}$, you can get, while maintaining the voltage gain, $\left|A_{v}\right|>40$, for an output swing of at least $400\mathrm {mV}$, $C_{L}=5pF$, and an output DC voltage of $0.9\mathrm {V}$.

You are to submit:

• A short description of the design procedure you used to obtain $V^{*}$, $I_{D}$, $W$, and $L$.
• Any calculations you have done.
• A DC sweep of $v_{out}$ vs. $v_{in}$.
  • What is the maximum symmetric output voltage swing for $\left|A_{v}\right|>40$?
  • What is the corresponding input voltage swing?
• A plot of the magnitude response showing the low frequency gain, and the unity-gain frequency.
  • What is the maximum $f_{T}$ you achieved? Can you think of applications that can use amplifiers with this $f_{T}$?
  • How much more current are you consuming compared to the amplifier in Part 1?

Part 3

You are now asked to design an amplifier with the lowest DC power consumption, $P_{DC}=V_{DD}\cdot I_{D}$, you can achieve, while maintaining the voltage gain, $\left|A_{v}\right|>40$, for an output swing of at least $400\mathrm {mV}$, $C_{L}=5pF$, and an output DC voltage of $0.9\mathrm {V}$.

You are to submit:

• A short description of the design procedure you used to obtain $V^{*}$, $I_{D}$, $W$, and $L$.
• Any calculations you have done.
• A DC sweep of $v_{out}$ vs. $v_{in}$.
  • What is the maximum symmetric output voltage swing for $\left|A_{v}\right|>40$?
  • What is the corresponding input voltage swing?
• A plot of the magnitude response showing the low frequency gain, and the unity-gain frequency.
  • What is the $f_{T}$ of your low-power amplifier?
  • Compare your bias current, $I_{D}$, to those obtained in Parts 1 and 2. Can you think of applications that can take advantage of these power levels?

Report Guide

Write up a report (maximum of 6 pages including figures) answering the questions above. Include annotated graphs if needed.

Submission

This activity is for both graduate and undergraduate students. For UP students, the submission bin link will be posted in Piazza.