EE220 2024 Noise Analysis and Simulation

• Instructions: This activity is structured as a tutorial with an activity at the end. Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
• At the end of this activity, the student should be able to:

1. Perform noise simulations using Cadence Spectre using the GlobalFoundries 22nm FDSOI design kit.

Activity 1: NMOS Noise

Bias a 0.8V SLVT NMOS transistor with $V_{GS}=0.4\mathrm {V}$ and $V_{DS}=0.4\mathrm {V}$. For a width of $1\mathrm {\mu m}$ and a length of $L_{\min }$:

• What is the resulting DC drain current?
• What is the transistor's $g_{m}$ and $V^{*}={\frac {2I_{D}}{g_{m}}}$?

Run a noise analysis from $1\mathrm {Hz}$ to $100\mathrm {GHz}$.

• Plot the drain current noise power spectral density, ${\frac {\overline {i_{dn}^{2}\left(f\right)}}{\Delta f}}$.
  • Identify the regions where thermal noise and flicker noise dominates.
  • What is the flicker noise corner?
  • Estimate the value of $\gamma$.
  • Estimate the value of ${\frac {K_{f}}{C_{ox}}}$
• What is the total integrated drain current noise power?

Recall that the MOSFET drain current noise can be modeled as:

${\overline {i_{dn}^{2}}}={\frac {K_{f}I_{D}}{C_{ox}L^{2}}}{\frac {\Delta f}{f}}+4kT\gamma g_{m}\Delta f$

Change the length of the transistor to $2L_{\min }$ and $3L_{\min }$. Identify and explain any changes in the drain current noise power spectral density.

Activity 2: PMOS Noise

Repeat Activity 1 but with a 0.8V SLVT PMOS transistor with the same size and with $V_{GS}=-0.4\mathrm {V}$ and $V_{DS}=-0.4\mathrm {V}$.