User contributions for Anastacia Alvarez

09:4009:40, 24 April 2024 diff hist +1‎ Lab 4: Sequential Design ‎No edit summary Tag: Visual edit
09:3809:38, 24 April 2024 diff hist +566‎ Lab 4: Sequential Design ‎No edit summary
08:3508:35, 24 April 2024 diff hist 0‎ Project Discussion ‎No edit summary
08:3408:34, 24 April 2024 diff hist +48‎ Project Discussion ‎No edit summary
08:3308:33, 24 April 2024 diff hist +236‎ Project Discussion ‎No edit summary
08:3008:30, 24 April 2024 diff hist +377‎ N Project Discussion ‎ Created page with "For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual. Some possible projects (for undergrads): * 8- or 16- bit processor * image filtering * other encryption/decryption algorithms"
08:2708:27, 24 April 2024 diff hist +4‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
08:2608:26, 24 April 2024 diff hist +102‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline

15:0715:07, 22 April 2024 diff hist +24‎ Lab 4: Sequential Design ‎No edit summary
13:0513:05, 22 April 2024 diff hist +25‎ Lab 4: Sequential Design ‎No edit summary
13:0413:04, 22 April 2024 diff hist +358‎ N Lab 4: Sequential Design ‎ Created page with "In this exercise, we will complete our design of the LiCi encryption. Below are the general steps we will be following: * Using the keygen design from Lab 2, we will re-synthesize it using the sky130nm following the procedure in Lab 3. * Design the whole system, using our keygen, LiCi round and counter. * Synthesize the design with and without constraints"
13:0013:00, 22 April 2024 diff hist +2‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
13:0013:00, 22 April 2024 diff hist +2‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline

14:0814:08, 19 March 2024 diff hist +3‎ DFG Exercise ‎No edit summary current
14:0714:07, 19 March 2024 diff hist +342‎ N DFG Exercise ‎ Created page with "Given the following code snippet: d = a*c t = a+b s = d*t If t = 1 then { d = a-b s = a+b } Else d = a+d 1. Determine the single assignment form of the code 2. Draw the corresponding data flow graph 4. Determine the datapath assuming you have 1 multiplier, 1 adder and 1 subtractor 5. Derive the corresponding control"
14:0314:03, 19 March 2024 diff hist +18‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline

18:2318:23, 14 March 2024 diff hist −91‎ Lab 3a: Synthesis and P&R ‎No edit summary current
18:2218:22, 14 March 2024 diff hist +635‎ Lab 3a: Synthesis and P&R ‎No edit summary
18:1618:16, 14 March 2024 diff hist +148‎ N Lab 3a: Synthesis and P&R ‎ Created page with "In this exercise, we will go through the synthesis and place and route process with the SkyWater 130nm process. Use the tutorial from SEACAS 2023."
18:1418:14, 14 March 2024 diff hist +32‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline

14:4914:49, 26 February 2024 diff hist −8‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
14:4714:47, 26 February 2024 diff hist +107‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
14:3214:32, 26 February 2024 diff hist +861‎ N Hardware Description Languages ‎ Created page with "As the size and complexity of digital systems increase, more computer aided design tools which facilitate design entry, verification and automatic hardware generation are being introduced into the design process. The newest addition to this design methodology is Hardware Description Languages (HDLs). Hardware Description Language is a specialized language used to describe the behaviour and/or structure of digital circuits. HDLs are used to describe hardware for the pur..."

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