SEACAS Chipathon 2023: Difference between revisions
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== About == | |||
The IEEE Republic of Philippines Section Solid-State Circuits Society (SSCS) Chapter and CAS/SP Joint Chapter are happy to announce the SEACAS and Student Chipathon 2023, which will be held in Quezon City, Philippines on '''18-19 September 2023'''. This year it will be a Chapthon instead of a Hackathon where students will be able to experience the whole integrated circuit (IC) design flow using open-source tools. Details of the event, the tools and mechanics of the Chipathon will be available in this website. | The IEEE Republic of Philippines Section Solid-State Circuits Society (SSCS) Chapter and CAS/SP Joint Chapter are happy to announce the SEACAS and Student Chipathon 2023, which will be held in Quezon City, Philippines on '''18-19 September 2023'''. This year it will be a Chapthon instead of a Hackathon where students will be able to experience the whole integrated circuit (IC) design flow using open-source tools. Details of the event, the tools and mechanics of the Chipathon will be available in this website. | ||
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18:00-20:00 - (Dinner) | 18:00-20:00 - (Dinner) | ||
''Sept 19, 2023 (Day 2) - Student | ''Sept 19, 2023 (Day 2) - Student Chipathon'' | ||
10:00-12:00 - Chipathon continues | 10:00-12:00 - Chipathon continues | ||
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18:00-20:00 - Dinner | 18:00-20:00 - Dinner | ||
== Chipathon Mechanics == | |||
==== Scope ==== | |||
he students from each chapter will be formed into groups of rwo (2) and they will be asked to design and implement a certain algorithm (e.g. FFT, LMS filtering, Reed-Solomon's coding, etc), the exact algorithm will be announce day of the event, but the necessary software and tools will be given at least a week before the event. An addition to the algorithm, an example or baseline design in RTL will be given as a demonstraton. | |||
==== Expectations to the students ==== | |||
# '''Digital Design'''. Students will use the digital (not analog) IC design flow. | |||
# '''Minimum requirements'''. Each team needs to produce a GDS layout of the baseline design, the design has to be functionally correct, clear DR and LVS. | |||
# '''Additional design credit'''. Each team is free to implement any modifications / optimizaation to the baseline to improve the design, and the team will be given credits for any improvement (power, performance, area, etc). | |||
# '''Reports'''. Each team is also expected to be able to generate the following reports: Utilization ratio, Critical path, Area, DRC, violations, etc | |||
==== Participant Requirements ==== | |||
# Basic knowledge of electronics and digital circuits. | |||
# Basic knowledge on digital design flow. | |||
Revision as of 13:43, 17 July 2023
About
The IEEE Republic of Philippines Section Solid-State Circuits Society (SSCS) Chapter and CAS/SP Joint Chapter are happy to announce the SEACAS and Student Chipathon 2023, which will be held in Quezon City, Philippines on 18-19 September 2023. This year it will be a Chapthon instead of a Hackathon where students will be able to experience the whole integrated circuit (IC) design flow using open-source tools. Details of the event, the tools and mechanics of the Chipathon will be available in this website.
Tentative Schedule
Sept 18, 2023 (Day 1) - SEACAS & Student Chipathon
10:00-12:00 - A discussion on Open-source tools and IC design that will be used in the Chipathon
- Student Chipathon starts
12:00-14:00 - Lunch SEACAS participants (officers and students)
14:00-16:00 - Research presentations by Chapter Officers
18:00-20:00 - (Dinner)
Sept 19, 2023 (Day 2) - Student Chipathon
10:00-12:00 - Chipathon continues
12:00-14:00 - Lunch SEACAS participants (officers and students)
14:00-15:30 - Hackathon presentation/judging
15:30-16:00 - Hackathon Award Ceremony
18:00-20:00 - Dinner
Chipathon Mechanics
Scope
he students from each chapter will be formed into groups of rwo (2) and they will be asked to design and implement a certain algorithm (e.g. FFT, LMS filtering, Reed-Solomon's coding, etc), the exact algorithm will be announce day of the event, but the necessary software and tools will be given at least a week before the event. An addition to the algorithm, an example or baseline design in RTL will be given as a demonstraton.
Expectations to the students
- Digital Design. Students will use the digital (not analog) IC design flow.
- Minimum requirements. Each team needs to produce a GDS layout of the baseline design, the design has to be functionally correct, clear DR and LVS.
- Additional design credit. Each team is free to implement any modifications / optimizaation to the baseline to improve the design, and the team will be given credits for any improvement (power, performance, area, etc).
- Reports. Each team is also expected to be able to generate the following reports: Utilization ratio, Critical path, Area, DRC, violations, etc
Participant Requirements
- Basic knowledge of electronics and digital circuits.
- Basic knowledge on digital design flow.