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(Created page with "Exercise on Timing. A single pipeline processor operating at 1V is depicted in the figure below: a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions? b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor.") |
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A single pipeline processor operating at 1V is depicted in the figure below: | A single pipeline processor operating at 1V is depicted in the figure below: | ||
[[File:Timing-pipeline.PNG]] | |||
a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions? | |||
b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor. | b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor. | ||
Revision as of 15:30, 4 December 2023
Exercise on Timing.
A single pipeline processor operating at 1V is depicted in the figure below:
a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions?
b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor.