Lab 4: Sequential Design

In this exercise, we will complete our design of the LiCi encryption. Below are the general steps we will be following:

• Using the keygen design from Lab 2, we will re-synthesize it using the sky130nm following the procedure in Lab 3. Since the design is purely combinational (therefore no CLK requirements), and we just want to check for synthesizability of the code, you can retain only the following lines in your config file (the rest can be removed):

   "DESIGN_NAME": 
   "VERILOG_FILES": 
   "FP_PDN_VOFFSET": 
   "FP_PDN_HOFFSET": 
   "FP_PDN_SKIPTRIM": 
   "FP_CORE_UTIL": 

Note that you will need to specify the correct design name and verilog files to be used. For the core utilization, increase it to 0.7.

• Design the whole system, using our keygen, LiCi round and counter. You might also need a control block to facilitate the flow of signals. Note also that the S-box for the keygen is different from the S-box of the LiCi round.
• Simulate your design and see that it is working as intended using behavioural simualtion
• Synthesize the design this time, updating your config file for a 50MHz clock, and setting input pins to the top and left side while placing output pins on the right side.

You are to submit the following:

1. A report containing the following:

• The characterization of the re-synthesized keygen
• Block diagram of the whole system
• The characterization of the whole system
• Discussion and analysis

Also include a discussion of your constraints in your report. Check the openlane documentation and determine the default values for clock uncertainty and other relevant timing parameters. How will changing these values affect your design and its performance?

2. Your verilog codes of your design and testbenches and a text file containing your config for the constraints. Include a text file describing each file.

3. Relevant reports from tool to support your characterization in the report

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