Modern VLSI Design (February 2024)

• Modern VLSI Design
• Second Semester AY 2023-2024
  • Synchronous classes will be held Tuesdays 6:30-8:30 PM from 20 Feb 2024 - 21 May 2024
  • Refer to the UP Diliman Academic Calendar for relevant dates and holidays.
• Course Credit: 3 units (2 units lecture, 1 unit lab)

Catalog Description

Digital systems and VLSI. Transistors and layout. Logic functions. Combinational logic networks. Sequential machines. Systems architecture design and HDLs. Subsystem design and IP components. CAD systems and algorithms.

Prerequisite: Switching Theory and Digital Logic Design

Course Outline

Module	Date	Topic	Resources	Activity
0	Feb 13	Class Policies	syllabus
1	Feb 20	Introduction to Digital Systems and VLSI	Video Recording EDA Playground Tutorial	Tool Orientation
2-3	Feb 27	Hardware Description Languages	Part1 Video Recording Part2 Video Recording	Lab 1a: Synthesis Lab 1b: Coding Styles Lab 2: Combinational Design
4-5	March 12	Architectural Design	ASM Video Recording Programmable Devices Discussion Recording	Lab 3a: Synthesis and P&R DFG Exercise
		Lenten + Reading Break
6	April 16	Timing and Sequential Circuits	Timing Video Recording	Lab 4: Sequential Design Project Discussion
7	April 23	Design Process Transistors	Lecture Recording
8	April 30	Logic Functions	Video lecture part 1
9	May 7	Testing and Testability	Test economics
10	May 14	Design for Test	Lecture recording

Announcements

• May 15: We extend our thanks again to Mr. Chris Vincent Densing of Embedded Silicon for his time and sharing his knowledge on DFT; the recording of the lecture is now uploaded
• May 14: Uploaded new video recordings; Lab 4 instructions updated
• April 17: Video recording for April 16 now uploaded.
• March 15: Video recording for March 14 now uploaded. Link to Lab 3a (Synthesis and P&R) also added.
• March 12: To give time to those who have not finished Lab 1a and Lab 1b yet, we will swap the lec and lab schedules this week. We will meet for lecture on Thursday (March 14) instead of today.
• March 8: Please note that Lab 1a is due this Saturday (March 9). Also the counter should be synchronous with clk. That is, 'en' is sampled every edge of the clock (not every transition of en).
• March 6: Lab exercise on combinational design now uploaded. March 5 recording also now available.
• February 28: Lab exercise on coding styles now uploaded. For Feb 29, the activities would be to perform Lab 1a and Lab 1b.
• February 22: Here's a simple [Icarus Verilog Tutorial] you may use
• February 21: As suggested by one of your classmates (thanks, Fides!) you can also try using [Icarus Verilog] (free to download) for the verilog simulator
• February 21: Video recording of Lec 1 (Introduction) now uploaded. For Thursday (Feb 22), there will be no synchronous meeting. Please try the EDA Playground Tutorial.
• February 19: Students enlisted in EE 227 and CoE 197-JB are now added in the UVLe. Be sure to accomplish the agreements and syllabus conforme.

References

• review of semiconductor fundamentals [EEE 41]

• Book References
  • S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd ed., McGraw Hill: New York, 2014
  • M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits, Springer: Boston, 2002
  • M. Keating, D. Flynn, R. Aitken, A. Gibbons, K. Shi, Low Power Methodology Manual (For System-on-Chip Design), Springer, 2007
  • J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Second edition, Prentice Hall, 2002.
  • N. Weste, D. Harris, CMOS VLSI Design (A Circuits and Systems Perspective), Addison-Wesley, 2005
  • W. Wolf, Modern VLSI Design: IP-Based Design, Fourth edition, Pearson Education Inc., 2009

• Other References