Project Discussion: Difference between revisions
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(Created page with "For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual. Some possible projects (for undergrads): * 8- or 16- bit processor * image filtering * other encryption/decryption algorithms") |
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For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual. | For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual. | ||
Some possible projects (for undergrads): | Some possible projects (for undergrads): | ||
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* image filtering | * image filtering | ||
* other encryption/decryption algorithms | * other encryption/decryption algorithms | ||
For grad students, your project would be implementing some image processing (background subtraction, object detection, feature extraction, etc) in HDL. | |||
Your designs are expected to be done in Verilog, synthesized, and characterized in terms of power, area and speed. You are to submit an IEEE-formatted paper for your report, and a zip file containing your design and testbench files. | |||
Back to [[Modern VLSI Design (February 2024)]] | |||
Latest revision as of 14:16, 7 May 2024
For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual.
Some possible projects (for undergrads):
- 8- or 16- bit processor
- image filtering
- other encryption/decryption algorithms
For grad students, your project would be implementing some image processing (background subtraction, object detection, feature extraction, etc) in HDL.
Your designs are expected to be done in Verilog, synthesized, and characterized in terms of power, area and speed. You are to submit an IEEE-formatted paper for your report, and a zip file containing your design and testbench files.