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Exercise on Timing. | '''Exercise on Timing, Power and Energy.''' | ||
A single pipeline processor operating at 1V is depicted in the figure below: | A single pipeline processor operating at 1V is depicted in the figure below: | ||
[[File:Timing-pipeline.PNG]] | [[File:Timing-pipeline.PNG|966x966px]] | ||
a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions? | a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions? | ||
b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor. | b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor. | ||
c. Compare the energy of the 3-stage processor with a multistage processor employing power gating such that only the energy of the registers needed remain (energy of other blocks is 0). | |||
Latest revision as of 15:42, 4 December 2023
Exercise on Timing, Power and Energy.
A single pipeline processor operating at 1V is depicted in the figure below:
a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions?
b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor.
c. Compare the energy of the 3-stage processor with a multistage processor employing power gating such that only the energy of the registers needed remain (energy of other blocks is 0).