Energy Efficient Machine Learning Hardware Co-design: Difference between revisions

From Center for Integrated Circuits and Devices Research (CIDR)
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| Supervising SRS || Sherry Joy Alvionne S. Baquiran
| Supervising SRS || Sherry Joy Alvionne S. Baquiran
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|-
| University Researcher || Fredrick Angelo Galapon
| rowspan="2" | University Researcher || Fredrick Angelo Galapon
|-  
|-
| || Allen Jason Tan
| Allen Jason Tan
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| Science Research Specialist || Maria Luz Limun
| Science Research Specialist || Maria Luz Limun
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|-
| Project Staff || Ryan Albert Antonio
| rowspan="3" | Project Staff || Ryan Albert Antonio
|-  
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| || Rhandley D. Cajote, PhD
| Rhandley D. Cajote, PhD
|-  
|-
| || Lawrence Roman Quizon
| Lawrence Roman Quizon
|}
|}


==Activities==
==Activities==
The project will have three major activities:
The project will have four (4) major activities:
#The development of IR-UWB transmitter system models for analysis, energy optimization, and automated circuit generation,
#Design and implementation WSN machine learning for clustering and routing
#The design, implementation, and verification of IR-UWB transmitter building blocks, and
#ISA-optimization of RISC-V processor for machine learning
#The design, implementation, and verification of a proof-of-concept IR-UWB transmitter, all in 28nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology.
#Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology.
#Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF)
==Resources==
==Resources==
*Tutorials
*Tutorials

Revision as of 09:32, 29 September 2022

This  component  project  of  the  CIDR  program tackles  the  co-design  of  energy-efficient  machine  learning algorithms and hardware. Methodologies to integrate machine learning on-chip for distributed data processing, network lifespan improvement and security will be explored. These methodologies will likewise pave the way for automated hardware generation for the accelerator needed to perform these tasks.

Personnel

Project Leader Anastacia B. Alvarez, PhD
Supervising SRS Sherry Joy Alvionne S. Baquiran
University Researcher Fredrick Angelo Galapon
Allen Jason Tan
Science Research Specialist Maria Luz Limun
Project Staff Ryan Albert Antonio
Rhandley D. Cajote, PhD
Lawrence Roman Quizon

Activities

The project will have four (4) major activities:

  1. Design and implementation WSN machine learning for clustering and routing
  2. ISA-optimization of RISC-V processor for machine learning
  3. Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology.
  4. Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF)

Resources

  • Tutorials
  • Scripts
  • Presentations
  • Papers