Modern VLSI Design (February 2024): Difference between revisions

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(Created page with "* '''Modern VLSI Design''' * Second Semester AY 2023-2024 ** Synchronous classes will be held Tuesdays 6:30-8:30 PM from 20 Feb 2024 - 21 May 2024 ** Refer to the [https://our.upd.edu.ph/files/calendar/regular/ACAD%20CAL%202023-2024.pdf UP Diliman Academic Calendar] for relevant dates and holidays. * Course Credit: 3 units (2 units lecture, 1 unit lab) == Catalog Description == Digital systems and VLSI. Transistors and layout. Logic functions. Combinational logic netwo...")
 
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== Course Outline ==
== Course Outline ==
{| class="wikitable" style="width: 70%;"
{| class="wikitable" style="width: 90%;"
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! Module !! Date !! Topic !! Resources !! Activity
! Module !! Date !! Topic !! Resources !! Activity
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| style="width: 5%"| 1 ||style="width: 10%"| 25 Sep 2023 ||style="width: 30%"| Introduction
| style="width: 5%"| 1 ||style="width: 10%"| Feb 13 ||style="width: 30%"| Class Policies
|| [[https://drive.google.com/file/d/1NbhtoP3g40WDHdIrsDwG6BdELkM1DL55/view?usp=sharing video]]
| style="width: 20%" |
|| [[Activity 1]]
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| 2 || 02 Oct 2023 || MOS Transistor and Technology Scaling
| 2 || Feb 20 || Introduction to Digital Systems and VLSI
|| [[https://drive.google.com/file/d/1NfmDr5wB-xRnDP-Zb-JWHkCWvscNsNI2/view?usp=sharing video]]
||  
|| [[Installing the Tools]]
|| Tool Orientation
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| 3 || 09 Oct 2023 || CMOS Inverter and Delay models
| 3-4 || Feb 27 || Hardware Description Languages
|| [[https://drive.google.com/file/d/197AJnFycvcV3W-9ipT3Mr58JRIR8uTlf/view?usp=sharing Inverter]]
||  
|| [[Activity 3]]
|| Lab 1: Coding Styles
 
Lab 2: Combinational Design
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| || 12-18 Oct 2023 || Reading Break
| 5-6 || March 12 || Architectural Design
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|| Lab 3: Timing Constraints
 
Lab 4: Sequential Design
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| 4 || 23 Oct 2023 || CMOS Gates and Logical Effort
| || || Lenten + Reading Break
|| [[https://drive.google.com/file/d/1Wt4LvZqdrq1CU_US9XoRVZBIAMs_QnJ8/view?usp=sharing CMOS Gates]]
[[https://drive.google.com/file/d/1WxqTbO4-tBACEPJNUPVA_fz1UL5KrkEu/view?usp=sharing Logical Effort]]
|| [[CMOS Gates Exercise]]
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| || 30 Oct 2023 || Declared Non-working Holiday
| 7 || April 9 || Transistors
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|| Project Discussion
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| 5 || 6 Nov 2023 || Variability
| 8 || April 16 || Logic Functions
|| [[https://drive.google.com/file/d/1AEda5iR8LFU87qcRtVnkg2rD0idrtuSS/view?usp=sharing pre-recorded video]]
||  
[[https://www.youtube.com/watch?v=JfNnSYuIOkc Security]]
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| 6 || 13 Nov 2023 || Low power design techniques
| 9 || April 23 || Logic Network
|| [[https://drive.google.com/file/d/1_Q7BYbCAP3o_j4wjul-ODRj5SN2FDwdQ/view?usp=sharing Power video]]
||  
[[https://drive.google.com/file/d/1_FSKjfoFh_GVyawRaalENyBKW2FqcY43/view?usp=sharing Energy video]]
||  
|| [[Lab Exercise on Variability]]
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| 7 || 20 Nov 2023 || Timing
|| [[https://drive.google.com/file/d/1BV0ttfCVDo5EpB0V9iViTK9UlsCgwOwt/view?usp=sharing video]]
|| [[Activity 7]]
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| || 27 Nov 2023 || Declared Holiday
| 10 || April 30 || Sequential Circuits
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| 8 || 4 Dec 2023 || Memory Design
| 11 || May 7 || Testing and Testability
|| [[https://drive.google.com/file/d/1aoxYZsKu5IOTHL_aaU10Nv5KgLD7TVU5/view?usp=sharing video]]
|| [[Lab Exercise on Memory]]
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| 9 || 11 Dec 2023 || Subthreshold Memory
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| 10 || 18 Dec 2023 || One-on-one project discussions
| 12 || May 14 || Design for Test
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|  || 8 Jan 2024 || Finals
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|}
|}


Revision as of 15:24, 13 February 2024

  • Modern VLSI Design
  • Second Semester AY 2023-2024
    • Synchronous classes will be held Tuesdays 6:30-8:30 PM from 20 Feb 2024 - 21 May 2024
    • Refer to the UP Diliman Academic Calendar for relevant dates and holidays.
  • Course Credit: 3 units (2 units lecture, 1 unit lab)

Catalog Description

Digital systems and VLSI. Transistors and layout. Logic functions. Combinational logic networks. Sequential machines. Systems architecture design and HDLs. Subsystem design and IP components. CAD systems and algorithms.

Prerequisite: Switching Theory and Digital Logic Design

Course Outline

Module Date Topic Resources Activity
1 Feb 13 Class Policies
2 Feb 20 Introduction to Digital Systems and VLSI Tool Orientation
3-4 Feb 27 Hardware Description Languages Lab 1: Coding Styles

Lab 2: Combinational Design

5-6 March 12 Architectural Design Lab 3: Timing Constraints

Lab 4: Sequential Design

Lenten + Reading Break
7 April 9 Transistors Project Discussion
8 April 16 Logic Functions
9 April 23 Logic Network
10 April 30 Sequential Circuits
11 May 7 Testing and Testability
12 May 14 Design for Test

References

  • review of semiconductor fundamentals [EEE 41]
  • review of transistors and transistor circuits [EEE 51]
  • Boom References
    • S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd ed., McGraw Hill: New York, 2014
    • M. Bushnell and V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits, Springer: Boston, 2002
    • M. Keating, D. Flynn, R. Aitken, A. Gibbons, K. Shi, Low Power Methodology Manual (For System-on-Chip Design), Springer, 2007
    • J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, Second edition, Prentice Hall, 2002.
    • N. Weste, D. Harris, CMOS VLSI Design (A Circuits and Systems Perspective), Addison-Wesley, 2005
    • W. Wolf, Modern VLSI Design: IP-Based Design, Fourth edition, Pearson Education Inc., 2009


  • Other References
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