Lab 4: Sequential Design: Difference between revisions
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You are to submit the following: | You are to submit the following: | ||
1. A report containing the following: | 1. A report containing the following: | ||
* The characterization of the re-synthesized keygen | |||
* Block diagram of the whole system | |||
* The characterization of the whole system | |||
* Discussion and analysis | |||
2. Your verilog codes of your design and testbenches. Include a text file describing each file. | 2. Your verilog codes of your design and testbenches. Include a text file describing each file. | ||
3. Relevant reports from tool to support your characterization in the report | 3. Relevant reports from tool to support your characterization in the report | ||
Back to [[Modern_VLSI_Design_(February_2024)]] | Back to [[Modern_VLSI_Design_(February_2024)]] |
Revision as of 09:40, 24 April 2024
In this exercise, we will complete our design of the LiCi encryption. Below are the general steps we will be following:
- Using the keygen design from Lab 2, we will re-synthesize it using the sky130nm following the procedure in Lab 3.
- Design the whole system, using our keygen, LiCi round and counter. You might also need a control block to facilitate the flow of signals. Note also that the S-box for the keygen is different from the S-box of the LiCi round.
- Synthesize the design with and without constraints
You are to submit the following:
1. A report containing the following:
- The characterization of the re-synthesized keygen
- Block diagram of the whole system
- The characterization of the whole system
- Discussion and analysis
2. Your verilog codes of your design and testbenches. Include a text file describing each file.
3. Relevant reports from tool to support your characterization in the report