Digital Systems Testing (January 2025)

• Digital Systems Testing
• Second Semester AY 2024-2025
  • Synchronous classes will be held Thursdays 6-9 PM
  • Refer to the UP Diliman Academic Calendar for relevant dates and holidays.
• Course Credit: 3 units (3 hours lecture)

Catalog Description

Test economics and motivation.  Fault models and simulation.  Test pattern generation.  Measures for testability.  Design for testability.  Memory testing.

Prerequisite: Digital Logic Design and Introduction to Semiconductor Devices

Course Outline

Module	Date	Topic	Resources	Activity
0	Jan 23	Introduction	Zoom Meeting Summary Lec00 Slide deck Meeting Recording
1	Jan 30	Economics of Test	Lec01 Slide deck Lec02 Slide deck Meeting Recording	Journal and Quiz (in UVLe)
2	Feb 6	Fault models	Lec03 Self Review Lec04 Slide deck Lec05 Slide deck Meeting Recording	Homework (from Lec04)
2	Feb 13	Algorithms for fault testing	Exercises Lec07 Slide Deck Meeting Recording
3	Feb 20	Sequential circuit testing	Lec08 Slide Deck Lec 09 Slide Deck Meeting Recording	Homework
3	Feb 27	Fault Detection in Sequential Circuits	Lec10 Time-Frame Expansion Meeting Recording	UVLe Quiz
4	Mar 6	Design for Test
4	Mar 13	Built-in Self-Test
5	Mar 20	Memory Testing
6	Mar 27	SCOAP Measurements

Announcements

• Feb 24: Last meeting's recording is now uploaded. Since we were not able to do the exercises last time, we will continue with the exercises on Thursday. The Homework will be moved as well.
• Feb 6: The meeting on Feb 13 will be in hybrid mode. Those attending the face-to-face meeting can proceed to Rm 307 for our class.
• Jan 23: This will be our class home page. For those enrolled in EE 269, assessment submissions will be through UVLe

References

• Book References
  • M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Springer, 2005.
  • Miron Abramovici, Melvin A. Breuer and  Arthur D. Friedman, “Digital Systems Testing & Testable Design”, IEEE Press, 1994
  • Niraj Jha and Sandeep Gupta, “Testing of Digital Systems”, Cambridge University Press, 2003
  • Z. Navabi, “Digital System Test and Testable Design”. Springer, 2011.

• Other References
  • Lukac, M., Kameyama, M., Perkowski, M., & Kerntopf, P. (2019). USING HOMING, SYNCHRONIZING AND DISTINGUISHING INPUT SEQUENCES FOR THE ANALYSIS OF REVERSIBLE FINITE STATE MACHINES. Facta Universitatis, Series: Electronics and Energetics, 32(3), 417-438
  • I. Pomeranz and S. Reddy, “Application of homing sequences to synchronous sequential circuit testing,” in Test Symposium, 1993., Proceedings of the Second Asian, pp. 324–329