Energy Efficient Machine Learning Hardware Co-design
This component project of the CIDR program tackles the co-design of energy-efficient machine learning algorithms and hardware. Methodologies to integrate machine learning on-chip for distributed data processing, network lifespan improvement and security will be explored. These methodologies will likewise pave the way for automated hardware generation for the accelerator needed to perform these tasks.
Personnel
| Project Leader | Anastacia B. Alvarez, PhD |
| Supervising SRS | Sherry Joy Alvionne S. Baquiran |
| University Researcher | Fredrick Angelo Galapon |
| Allen Jason Tan | |
| Science Research Specialist | Maria Luz Limun |
| Project Staff | Ryan Albert Antonio |
| Rhandley D. Cajote, PhD | |
| Lawrence Roman Quizon |
Activities
The project will have three major activities:
- The development of IR-UWB transmitter system models for analysis, energy optimization, and automated circuit generation,
- The design, implementation, and verification of IR-UWB transmitter building blocks, and
- The design, implementation, and verification of a proof-of-concept IR-UWB transmitter, all in 28nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology.
Resources
- Tutorials
- Scripts
- Presentations
- Papers