User contributions for Anastacia Alvarez

14:4914:49, 26 February 2024 diff hist −8‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
14:4714:47, 26 February 2024 diff hist +107‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
14:3214:32, 26 February 2024 diff hist +861‎ N Hardware Description Languages ‎ Created page with "As the size and complexity of digital systems increase, more computer aided design tools which facilitate design entry, verification and automatic hardware generation are being introduced into the design process. The newest addition to this design methodology is Hardware Description Languages (HDLs). Hardware Description Language is a specialized language used to describe the behaviour and/or structure of digital circuits. HDLs are used to describe hardware for the pur..."
14:3014:30, 26 February 2024 diff hist +4‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline

15:2515:25, 13 February 2024 diff hist −139‎ Modern VLSI Design (February 2024) ‎ →‎References
15:2415:24, 13 February 2024 diff hist −1,203‎ Modern VLSI Design (February 2024) ‎ →‎Course Outline
07:4007:40, 13 February 2024 diff hist +3,827‎ N Modern VLSI Design (February 2024) ‎ Created page with "* '''Modern VLSI Design''' * Second Semester AY 2023-2024 ** Synchronous classes will be held Tuesdays 6:30-8:30 PM from 20 Feb 2024 - 21 May 2024 ** Refer to the [https://our.upd.edu.ph/files/calendar/regular/ACAD%20CAL%202023-2024.pdf UP Diliman Academic Calendar] for relevant dates and holidays. * Course Credit: 3 units (2 units lecture, 1 unit lab) == Catalog Description == Digital systems and VLSI. Transistors and layout. Logic functions. Combinational logic netwo..."
07:3507:35, 13 February 2024 diff hist +41‎ Classes ‎ →‎Class Offerings Tag: Visual edit: Switched

21:3821:38, 15 December 2023 diff hist +2‎ Lab Exercise on Memory ‎No edit summary current Tag: Visual edit
21:3721:37, 15 December 2023 diff hist +244‎ N Lab Exercise on Memory ‎ Created page with "In this exercise, we will be designing a 6T SRAM 1. Start by determining the cell ratio (CR) and pull-up ratio (PR) of the SRAM 2. Characterize the SRAM by determine its noise margins 3. Determine Vmin (lowest VDD where SRAM is still function)"
18:0518:05, 15 December 2023 diff hist −14‎ Digital IC Design (September 2023) ‎ →‎Course Outline

17:5217:52, 14 December 2023 diff hist +267‎ N Lab Exercise on Variability ‎ Created page with "In this exercise, we want to investigate variations in an inverter. # Using the properly sized inverter, plot the histogram of the inverter propagation delays. # Do the same for a 4x inverter (both nmos and pmos are 4x larger than the original). How do they compare?" current Tag: Visual edit

15:4215:42, 4 December 2023 diff hist +221‎ Activity 7 ‎No edit summary current Tag: Visual edit
15:3015:30, 4 December 2023 diff hist +29‎ Activity 7 ‎No edit summary
15:1715:17, 4 December 2023 diff hist 0‎ N File:Timing-pipeline.PNG ‎No edit summary current
15:1315:13, 4 December 2023 diff hist +341‎ N Activity 7 ‎ Created page with "Exercise on Timing. A single pipeline processor operating at 1V is depicted in the figure below: a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions? b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor."

21:0921:09, 23 October 2023 diff hist +194‎ Digital IC Design (September 2023) ‎ →‎Course Outline
07:4407:44, 23 October 2023 diff hist +733‎ N CMOS Gates Exercise ‎ Created page with "Part 1. Transistor stacking: * Read the reference K. von Arnim, C. Pacha, K. Hofmann, T. Schulz, K. Schrufer and J. Berthold, "An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits," 2007 IEEE International Electron Devices Meeting, 2007, pp. 483-486, doi: 10.1109/IEDM.2007.4418979. * Write a short critique of the paper. * Try replicating their work. How would you size the NAND2 and NAND3 gates? Part 2. CMOS gate Consider the..." current
07:3007:30, 23 October 2023 diff hist +16‎ Digital IC Design (September 2023) ‎ →‎Course Outline

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