Activity: MOS Design Parameters

• Instructions: This activity is structured as a tutorial with an activity at the end. Should you have any questions, clarifications, or issues, please contact your instructor as soon as possible.
• At the end of this activity, the student should be able to:

1. Obtain the small signal design parameters of NMOS and PMOS transistors.

Activity 1: Small Signal Models

Figure 1: The MOS low-frequency small signal model.

Most of the time, we are interested in the small signal behavior of our amplifiers, i.e. what happens to the amplifier voltages and currents as we introduce small disturbances (information carrying signals) at the input. To gain intuition and to facilitate circuit analysis using nonlinear devices, we linearize our circuits to obtain the two-port model shown in Fig. 1. For MOSFETs at low frequencies, the two-port model is composed of the transconductance, and the output resistance.

Transconductance

Transconductance is defined as:

$g_{m}={\frac {\partial I_{D}}{\partial V_{GS}}}$

This is the slope of the transfer characteristic curves. Thus, by numerically differentiating the $I_{D}$ vs. $V_{GS}$ curve shown in Fig. 2 for an NMOS transistor with a width $W=10\mathrm {\mu m}$, a length $L=0.15\mathrm {\mu m}$, and with $nf=1$, we can obtain the transconductance plot shown in Fig. 3.

Figure 2: The NMOS transfer characteristics.

Figure 3: NMOS transconductance.

Output Resistance

Similarly, we can take the derivative of the output characteristics, shown in Fig. 4 for $V_{GS}=0.90\mathrm {V}$, to get the output resistance, which is defined as:

$r_{o}=\left({\frac {\partial I_{D}}{\partial V_{DS}}}\right)^{-1}$

The output resistance as a function of $V_{DS}$ is shown in Fig. 5 for $V_{GS}=0.90\mathrm {V}$.

Figure 4: NMOS output characteristic for $V_{GS}=0.90\mathrm {V}$.

Figure 5: NMOS output resistance for for $V_{GS}=0.90\mathrm {V}$.

Answer the following questions:

1. Given the transconductance plot in Fig. 3, why is there a peak in the transconductance curve? What is causing this?
2. Generate Fig. 3, but on a logarithmic y-axis. Is this what you expect for $V_{GS}<V_{TH}$? Explain.
3. Plot $g_{m}$ for $V_{DS}=0.45\mathrm {V}$ and $V_{DS}=1.35\mathrm {V}$. Does the transconductance change with $V_{DS}$? Is this the behavior you expect? Explain.
4. Plot the output resistance for $V_{GS}=0.45\mathrm {V}$ and $V_{GS}=0.1.35\mathrm {V}$. Do you see any changes in the the effects of process variations? What do you think is causing this behavior?

Activity 2: Power Efficiency

We can define a power efficiency figure of merit (FoM) for our transistors that quantifies the DC current cost, i.e. $I_{D}$, of achieving a certain transconductance, $g_{m}$. Mathematically, we can express this as ${\frac {g_{m}}{I_{D}}}$, and is plotted vs. $V_{GS}$, as shown in Fig. 6.

Figure 6: NMOS ${\frac {g_{m}}{I_{D}}}$.

Figure 7: NMOS $V_{ov}={\frac {2\cdot I_{D}}{g_{m}}}$.

An alternative form of this power efficiency metric, is $V^{*}=V_{ov}={\frac {2\cdot I_{D}}{g_{m}}}$. This alternative FoM is plotted against $V_{GS}$, as shown in Fig. 7.

Answer the following questions:

1. Why does the plot ${\frac {g_{m}}{I_{D}}}$, shown in Fig. 6, flatten out at low $V_{GS}$?
2. Recreate Fig. 6 but with $L=0.20\mathrm {\mu m}$ and $L=0.30\mathrm {\mu m}$. Does the maximum value of ${\frac {g_{m}}{I_{D}}}$ change? Is this what you expect? Why or why not?

Activity 3: Aggregate Figure of Merit

Figure 8: NMOS $f_{T}\cdot {\frac {g_{m}}{I_{D}}}$ vs. $V_{GS}$.

Figure 9: NMOS $f_{T}\cdot {\frac {g_{m}}{I_{D}}}$ vs. $V_{ov}$.

Activity 4: PMOS Small Signal Parameters

Repeat Activities 1, 2, and 3 for a 1.8V LVT PMOS transistor with a width $W=10\mathrm {\mu m}$, a length $L=0.35\mathrm {\mu m}$, and with $nf=1$.