RISC-V processor for machine learning

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Incorporating machine learning capabilities in wireless sensor networks (WSNs) will require an increase of computational capabilities of the sensor nodes. However, most WSNs use commercial, off-the-shelf Microcontroller Units (MCUs) that are low cost and have low power consumption but have limited processing capabilities[1] or System on Chips (SoCs) with high performance and low power consumption but has fixed configuration.[2] Due to these constraints, FPGA-based processors are currently being considered due to its rapid prototyping, dynamic reconfiguration, and acceleration of processing. It should be noted, though, that FPGA-based designs have greater power consumption as compared to SoC and MCU implementations. However, recent research shows that increasing computational capabilities at the network edge can shorten packet lengths, reduce sent packets[3], and reduce network usage, thus, significantly lowering the overall energy consumption of the sensor node.[4]

Figure 1. Project will implement an FPGA-based RISC-V Processor with Vector Extension.

To provide flexibility in the design of the processor, the RISC-V Instruction Set Architecture (ISA)[5], an open-source, royalty-free ISA, offers a simple, modular and stable architecture that is ideal for a wide variety of embedded and IoT applications. RISC-V implementation is composed of a mandatory base ISA called RV32I and a number of ISA extensions that can be added depending on the application that it will be used for. For machine learning applications, RISC-V has a vector extension suitable for parallel computations.

For this project, an FPGA-based RISC-V processor with vector extension will be implemented.

Baseline Processor Design

The design of the baseline processor is based on the paper of M.J. Neri, et al[6] from EEEI in the University of the Philippines, Diliman. It is an FPGA-based RISC-V processor with integer multiplication and division extension and compressed instruction extension, thus, an RV32IMC processor. The processor is pipelined with 5 stages as shown in Figure 2.

Figure 2. Top Level Block Diagram of the RV32IMC Processor.

Vector Extension

This section will be updated in the 2nd quarter of the project.

References

  1. ↑ F. Karray, M. W. Jmal, M. Abid, M. S. BenSaleh, and A. M. Obeid, “A Review on Wireless Sensor Node Architectures,” in 2014 9th International Symposium on Reconfigurable and CommunicationCentric Systems-on-Chip (ReCoSoC), May 2014, pp. 1–8.
  2. ↑ M. Maxfield, “ASIC, ASSP, SoC, FPGA - What’s the Difference?” EE Times, June 2014, [Online]. Available: https://www.eetimes.com/asic-assp-soc-fpga-whats-the-difference/#.
  3. ↑ V. Mihai, C. Dragana, G. Stamatescu, D. Popescu, and L. Ichim, “Wireless Sensor Network Architecture based on Fog Computing,” in 2018 5th International Conference on Control, Decision and Information Technologies (CoDIT), Apr. 2018, pp. 743–747.
  4. ↑ V. Mihai, C. E. Hanganu, G. Stamatescu, and D. Popescu, “WSN and Fog Computing Integration for Intelligent Data Processing,” in 2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), June 2018, pp. 1–4.
  5. ↑ RISC-V Specifications. [Online] https://riscv.org/technical/specifications/
  6. ↑ M. J. Neri, R. I. Ridao, V. E. Baylosis, P. M. Chua, A. J. Tan, “Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks,” in 2020 IEEE Region 10 Conference (TENCON), November 2020, pp. 806-8011.
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