CMOS Gates Exercise
Revision as of 07:44, 23 October 2023 by Anastacia Alvarez (talk | contribs) (Created page with "Part 1. Transistor stacking: * Read the reference K. von Arnim, C. Pacha, K. Hofmann, T. Schulz, K. Schrufer and J. Berthold, "An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits," 2007 IEEE International Electron Devices Meeting, 2007, pp. 483-486, doi: 10.1109/IEDM.2007.4418979. * Write a short critique of the paper. * Try replicating their work. How would you size the NAND2 and NAND3 gates? Part 2. CMOS gate Consider the...")
Part 1. Transistor stacking:
- Read the reference K. von Arnim, C. Pacha, K. Hofmann, T. Schulz, K. Schrufer and J. Berthold, "An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits," 2007 IEEE International Electron Devices Meeting, 2007, pp. 483-486, doi: 10.1109/IEDM.2007.4418979.
- Write a short critique of the paper.
- Try replicating their work. How would you size the NAND2 and NAND3 gates?
Part 2. CMOS gate Consider the logic function F = [AB + C(D + E)]'
- Draw the complementary CMOS implementation of F
- Indicate the correct sizes of the transistors
- Draw the stick diagram
- Assuming this logic function is implemented as a simple gate, what would its logical effort be?