Activity 7

Exercise on Timing, Power and Energy.

A single pipeline processor operating at 1V is depicted in the figure below:

a. Propose a 3-pipe stage version. Justify your solution. What would be the maximum clock period allowed for the single stage and 3-stage versions?

b. Discuss how moving from single stage to 3-pipe stage affects the energy of the processor.

c. Compare the energy of the 3-stage processor with a multistage processor employing power gating such that only the energy of the registers needed remain (energy of other blocks is 0).