Project Discussion

For your EE 227 project, each group/individual will be implementing a different design. Undergraduates are allowed to implement the project in groups of 2 or 3. Individual projects are also allowed. For graduate students, projects will be individual.

Some possible projects (for undergrads):

• 8- or 16- bit processor
• image filtering
• other encryption/decryption algorithms

Your designs are expected to be done in Verilog, synthesized, and characterized in terms of power, area and speed. You are to submit an IEEE-formatted paper for your report, and a zip file containing your design and testbench files.

Back to EE 227 Modern VLSI (February 2024)