Energy Efficient Machine Learning Hardware Co-design: Difference between revisions

From Center for Integrated Circuits and Devices Research (CIDR)
Jump to navigation Jump to search
 
(11 intermediate revisions by 2 users not shown)
Line 5: Line 5:
| Project Leader || Anastacia B. Alvarez, PhD
| Project Leader || Anastacia B. Alvarez, PhD
|-
|-
| Supervising SRS || Sherry Joy Alvionne S. Baquiran
| Senior Technical Specialist || Sherry Joy Alvionne S. Baquiran
|-
|-
| University Researcher || Fredrick Angelo Galapon
| rowspan="3" | Technical Specialist || Fredrick Angelo Galapon
|-
| || Allen Jason Tan
|-
|-
| Science Research Specialist || Maria Luz Limun
| Allen Jason Tan
|-
|-
| Project Staff || Ryan Albert Antonio
|Lawrence Roman Quizon
|-  
|-
| || Rhandley D. Cajote, PhD
| Administrative Officer || Maria Luz Limun
|-  
|-
| || Lawrence Roman Quizon
|Technical Aide
|Patrick Jake Valdez [Y1Q1-Y1Q3]
Andrei Gabriel Ay-ay [Y1-Q4]
|-
| rowspan="3" | Project Staff || Ryan Albert Antonio
|-
| Rhandley D. Cajote, PhD
|-
| John Francis Chan
|-
| rowspan="2" | Student Affiliate || Joenard Matanguihan
|-
| Randolf Tamayo
|}
|}


==Activities==
==Activities==
The project will have three major activities:
The project will have four (4) major activities:
#The development of IR-UWB transmitter system models for analysis, energy optimization, and automated circuit generation,
#Design and implementation WSN machine learning for [[clustering and routing]]
#The design, implementation, and verification of IR-UWB transmitter building blocks, and
#ISA-optimization of [[RISC-V processor for machine learning]]
#The design, implementation, and verification of a proof-of-concept IR-UWB transmitter, all in 28nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology.
#Design, implementation, and verification of a proof-of-concept [[distributed learning]] in 28nm FDSOI CMOS technology.
#Design and implementation of a proof-of-concept [[security module]] using physically unclonable functions (PUF)
==Resources==
==Resources==
*[[PSHS Internship 2023]]
*Tutorials
*Tutorials
*Scripts
*Scripts
*Presentations
*Presentations
*Papers
*Papers

Latest revision as of 18:49, 28 June 2023

This  component  project  of  the  CIDR  program tackles  the  co-design  of  energy-efficient  machine  learning algorithms and hardware. Methodologies to integrate machine learning on-chip for distributed data processing, network lifespan improvement and security will be explored. These methodologies will likewise pave the way for automated hardware generation for the accelerator needed to perform these tasks.

Personnel

Project Leader Anastacia B. Alvarez, PhD
Senior Technical Specialist Sherry Joy Alvionne S. Baquiran
Technical Specialist Fredrick Angelo Galapon
Allen Jason Tan
Lawrence Roman Quizon
Administrative Officer Maria Luz Limun
Technical Aide Patrick Jake Valdez [Y1Q1-Y1Q3]

Andrei Gabriel Ay-ay [Y1-Q4]

Project Staff Ryan Albert Antonio
Rhandley D. Cajote, PhD
John Francis Chan
Student Affiliate Joenard Matanguihan
Randolf Tamayo

Activities

The project will have four (4) major activities:

  1. Design and implementation WSN machine learning for clustering and routing
  2. ISA-optimization of RISC-V processor for machine learning
  3. Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology.
  4. Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF)

Resources

Retrieved from "https://cidr.up-microlab.org/index.php?title=Energy_Efficient_Machine_Learning_Hardware_Co-design&oldid=592"