Energy Efficient Machine Learning Hardware Co-design

This  component  project  of  the  CIDR  program tackles  the  co-design  of  energy-efficient  machine  learning algorithms and hardware. Methodologies to integrate machine learning on-chip for distributed data processing, network lifespan improvement and security will be explored. These methodologies will likewise pave the way for automated hardware generation for the accelerator needed to perform these tasks.

Personnel

Project Leader	Anastacia B. Alvarez, PhD
Senior Technical Specialist	Sherry Joy Alvionne S. Baquiran
Technical Specialist	Fredrick Angelo Galapon
	Allen Jason Tan
	Lawrence Roman Quizon
Administrative Officer	Maria Luz Limun
Technical Aide	Patrick Jake Valdez [Y1Q1-Y1Q3] Andrei Gabriel Ay-ay [Y1-Q4]
Project Staff	Ryan Albert Antonio
	Rhandley D. Cajote, PhD
	John Francis Chan
Student Affiliate	Joenard Matanguihan
	Randolf Tamayo

Activities

The project will have four (4) major activities:

1. Design and implementation WSN machine learning for clustering and routing
2. ISA-optimization of RISC-V processor for machine learning
3. Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology.
4. Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF)

Resources

• PSHS Internship 2023
• Tutorials
• Scripts
• Presentations
• Papers