Digital IC Design (August 2024): Difference between revisions

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| style="width: 5%"| 1 ||style="width: 10%"| 3 Sep 2024 ||style="width: 30%"| Introduction  
| style="width: 5%"| 1 ||style="width: 20%"| 10 Sep 2024 ||style="width: 30%"| Introduction  
|| [[video]]
|| [[video]]
|| [[Activity 1]]
|| [[Activity 1]]
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| 2 || 10 Sep 2024 || MOS Transistor and Technology Scaling
| 2 || 17 Sep 2024 || MOS Transistor and Technology Scaling
|| [[video]]
|| [[video]]
|| [[Installing the Tools]]
|| [[Installing the Tools]]
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| 3 || 17 Sep 2024 || CMOS Inverter and Delay models
| 3 || 24 Sep 2024 || CMOS Inverter and Delay models
|| [[ Inverter]]
|| [[ Inverter]]
|| [[Activity 3]]
|| [[Activity 3]]
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| || 12-18 Oct 2023 || Reading Break
| 4 || 1-8 Oct 2024 || CMOS Gates and Logical Effort
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| 4 || 23 Oct 2023 || CMOS Gates and Logical Effort
|| [[ CMOS Gates]]
|| [[ CMOS Gates]]
[[Logical Effort]]
[[Logical Effort]]
|| [[CMOS Gates Exercise]]
|| [[CMOS Gates Exercise]]
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|-  
|  || 30 Oct 2023 || Declared Non-working Holiday
|Midterm Exam
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|22 Oct 2024
| 5 || 6 Nov 2023 || Variability
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| 5 || 15 Oct 2024|| Arithmetic Circuits
|| [[video]]
||  
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| 6 || 29 Oct 2024|| Low power design techniques
|| [[video]]
|| [[video]]
[[Security]]
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| 6 || 13 Nov 2023 || Low power design techniques
| 7 || || Variability
|| [[Power video]]
|| [[video]]
[[Energy video]]
|| [[Lab Exercise on Variability]]
|| [[Lab Exercise on Variability]]
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| 7 || 20 Nov 2023 || Timing
| 8 || || Timing
|| [[video]]
|| [[video]]
|| [[Activity 7]]
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|  || 27 Nov 2023 || Declared Holiday
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| 8 || 4 Dec 2023 || Memory Design
| 9 || || Memory Design
|| [[video]]
|| [[video]]
|| [[Lab Exercise on Memory]]
|| [[Lab Exercise on Memory]]
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| 9 || 11 Dec 2023 || Subthreshold Memory
| 10 || || Testing and Testability
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| 10 || 18 Dec 2023 || One-on-one project discussions
| 11 || || Special Topics
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|  || 8 Jan 2024 || Finals
|| Finals
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Latest revision as of 07:43, 9 October 2024

  • First Semester AY 2024-2025
  • Course Credit: 4 units (3 units lecture, 1 unit lab)

Catalog Description

Fundamentals of MOSFETS. Technology and modelling. Scaling and limits of scaling. Design for deep-submicron CMOS – high speed. Design techniques for low power. Arithmetic circuits. Driving interconnect, high-speed signalling. Timing. Memory design. Design for testability.

Prerequisite: CoE 141 or equiv

Course Outline

Module Date Topic Resources Activity
1 10 Sep 2024 Introduction video Activity 1
2 17 Sep 2024 MOS Transistor and Technology Scaling video Installing the Tools
3 24 Sep 2024 CMOS Inverter and Delay models Inverter Activity 3
4 1-8 Oct 2024 CMOS Gates and Logical Effort CMOS Gates

Logical Effort

CMOS Gates Exercise
Midterm Exam 22 Oct 2024
5 15 Oct 2024 Arithmetic Circuits video
6 29 Oct 2024 Low power design techniques video
7 Variability video Lab Exercise on Variability
8 Timing video
9 Memory Design video Lab Exercise on Memory
10 Testing and Testability
11 Special Topics
Finals

References

  • review of semiconductor fundamentals [EEE 41]
  • review of transistors and transistor circuits [EEE 51]
  • Book References
    • J. Rabaey. 2009. Low Power Design Essentials. Springer Publishing Company, Incorporated.
    • J. Rabaey, Chandrakasan, A,, Nikolic, B. 2004. Digital integrated circuits- A design perspective. Prentice Hall.
    • A. Chandrakasan, W. Bowhill, and F. Fox. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press
    • M. Alioto (ed), Enabling the Internet of Things: From Integrated Circuits to Integrated Systems, Springer 2017.
    • Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA.
  • Other References