Energy Efficient Machine Learning Hardware Co-design: Difference between revisions
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==Activities== | ==Activities== | ||
The project will have four (4) major activities: | The project will have four (4) major activities: | ||
#Design and implementation WSN machine learning for clustering and routing | #Design and implementation WSN machine learning for [[clustering and routing]] | ||
#ISA-optimization of RISC-V processor for machine learning | #ISA-optimization of [[RISC-V processor for machine learning]] | ||
#Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology. | #Design, implementation, and verification of a proof-of-concept [[distributed learning]] in 28nm FDSOI CMOS technology. | ||
#Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF) | #Design and implementation of a proof-of-concept [[security module]] using physically unclonable functions (PUF) | ||
==Resources== | ==Resources== | ||
*Tutorials | *Tutorials | ||
Revision as of 10:49, 18 October 2022
This component project of the CIDR program tackles the co-design of energy-efficient machine learning algorithms and hardware. Methodologies to integrate machine learning on-chip for distributed data processing, network lifespan improvement and security will be explored. These methodologies will likewise pave the way for automated hardware generation for the accelerator needed to perform these tasks.
Personnel
| Project Leader | Anastacia B. Alvarez, PhD |
| Supervising SRS | Sherry Joy Alvionne S. Baquiran |
| University Researcher | Fredrick Angelo Galapon |
| Allen Jason Tan | |
| Science Research Specialist | Maria Luz Limun |
| Science Aide | Patrick Jake Valdez |
| Project Staff | Ryan Albert Antonio |
| Rhandley D. Cajote, PhD | |
| Lawrence Roman Quizon | |
| Student Affiliate | Joenard Matanguihan |
Activities
The project will have four (4) major activities:
- Design and implementation WSN machine learning for clustering and routing
- ISA-optimization of RISC-V processor for machine learning
- Design, implementation, and verification of a proof-of-concept distributed learning in 28nm FDSOI CMOS technology.
- Design and implementation of a proof-of-concept security module using physically unclonable functions (PUF)
Resources
- Tutorials
- Scripts
- Presentations
- Papers