Digital IC Design (August 2024): Difference between revisions
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(Created page with "* First Semester AY 2024-2025 ** Synchronous classes will be held Tuesdays 6-9 PM ** Refer to the [https://upd.edu.ph/academics/academic-calendar-2/ UP Diliman Academic Calendar] for relevant dates and holidays. * Course Credit: 4 units (3 units lecture, 1 unit lab) == Catalog Description == Fundamentals of MOSFETS. Technology and modelling. Scaling and limits of scaling. Design for deep-submicron CMOS – high speed. Design techniques for low power. Arithmetic circui...") |
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! Module !! Date !! Topic !! Resources !! Activity | ! Module !! Date !! Topic !! Resources !! Activity | ||
|- | |- | ||
| style="width: 5%"| 1 ||style="width: 10%"| | | style="width: 5%"| 1 ||style="width: 10%"| 3 Sep 2024 ||style="width: 30%"| Introduction | ||
|| [[ | || [[video]] | ||
|| [[Activity 1]] | || [[Activity 1]] | ||
|- | |- | ||
| 2 || | | 2 || 10 Sep 2024 || MOS Transistor and Technology Scaling | ||
|| [[ | || [[video]] | ||
|| [[Installing the Tools]] | || [[Installing the Tools]] | ||
|- | |- | ||
| 3 || | | 3 || 17 Sep 2024 || CMOS Inverter and Delay models | ||
|| [[ | || [[ Inverter]] | ||
|| [[Activity 3]] | || [[Activity 3]] | ||
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| 4 || 23 Oct 2023 || CMOS Gates and Logical Effort | | 4 || 23 Oct 2023 || CMOS Gates and Logical Effort | ||
|| [[ | || [[ CMOS Gates]] | ||
[[ | [[Logical Effort]] | ||
|| [[CMOS Gates Exercise]] | || [[CMOS Gates Exercise]] | ||
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| 5 || 6 Nov 2023 || Variability | | 5 || 6 Nov 2023 || Variability | ||
|| [[ | || [[video]] | ||
[[ | [[Security]] | ||
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| 6 || 13 Nov 2023 || Low power design techniques | | 6 || 13 Nov 2023 || Low power design techniques | ||
|| [[ | || [[Power video]] | ||
[[ | [[Energy video]] | ||
|| [[Lab Exercise on Variability]] | || [[Lab Exercise on Variability]] | ||
|- | |- | ||
| 7 || 20 Nov 2023 || Timing | | 7 || 20 Nov 2023 || Timing | ||
|| [[ | || [[video]] | ||
|| [[Activity 7]] | || [[Activity 7]] | ||
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| 8 || 4 Dec 2023 || Memory Design | | 8 || 4 Dec 2023 || Memory Design | ||
|| [[ | || [[video]] | ||
|| [[Lab Exercise on Memory]] | || [[Lab Exercise on Memory]] | ||
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* review of transistors and transistor circuits [[https://www.up-microlab.org/resources/classes/eee-51-home-page/eee-51-s2y2019/ EEE 51]] | * review of transistors and transistor circuits [[https://www.up-microlab.org/resources/classes/eee-51-home-page/eee-51-s2y2019/ EEE 51]] | ||
* | * Book References | ||
** J. Rabaey. 2009. Low Power Design Essentials. Springer Publishing Company, Incorporated. | ** J. Rabaey. 2009. Low Power Design Essentials. Springer Publishing Company, Incorporated. | ||
** J. Rabaey, Chandrakasan, A,, Nikolic, B. 2004. Digital integrated circuits- A design perspective. Prentice Hall. | ** J. Rabaey, Chandrakasan, A,, Nikolic, B. 2004. Digital integrated circuits- A design perspective. Prentice Hall. | ||
** A. Chandrakasan, W. Bowhill, and F. Fox. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press | ** A. Chandrakasan, W. Bowhill, and F. Fox. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press | ||
** M. Alioto (ed), Enabling the Internet of Things: From Integrated Circuits to Integrated Systems, Springer 2017. | |||
** Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA. | |||
* Other References | * Other References | ||
Revision as of 15:47, 1 September 2024
- First Semester AY 2024-2025
- Synchronous classes will be held Tuesdays 6-9 PM
- Refer to the UP Diliman Academic Calendar for relevant dates and holidays.
- Course Credit: 4 units (3 units lecture, 1 unit lab)
Catalog Description
Fundamentals of MOSFETS. Technology and modelling. Scaling and limits of scaling. Design for deep-submicron CMOS – high speed. Design techniques for low power. Arithmetic circuits. Driving interconnect, high-speed signalling. Timing. Memory design. Design for testability.
Prerequisite: CoE 141 or equiv
Course Outline
| Module | Date | Topic | Resources | Activity |
|---|---|---|---|---|
| 1 | 3 Sep 2024 | Introduction | video | Activity 1 |
| 2 | 10 Sep 2024 | MOS Transistor and Technology Scaling | video | Installing the Tools |
| 3 | 17 Sep 2024 | CMOS Inverter and Delay models | Inverter | Activity 3 |
| 12-18 Oct 2023 | Reading Break | |||
| 4 | 23 Oct 2023 | CMOS Gates and Logical Effort | CMOS Gates | CMOS Gates Exercise |
| 30 Oct 2023 | Declared Non-working Holiday | |||
| 5 | 6 Nov 2023 | Variability | video | |
| 6 | 13 Nov 2023 | Low power design techniques | Power video | Lab Exercise on Variability |
| 7 | 20 Nov 2023 | Timing | video | Activity 7 |
| 27 Nov 2023 | Declared Holiday | |||
| 8 | 4 Dec 2023 | Memory Design | video | Lab Exercise on Memory |
| 9 | 11 Dec 2023 | Subthreshold Memory | ||
| 10 | 18 Dec 2023 | One-on-one project discussions | ||
| 8 Jan 2024 | Finals |
References
- review of semiconductor fundamentals [EEE 41]
- review of transistors and transistor circuits [EEE 51]
- Book References
- J. Rabaey. 2009. Low Power Design Essentials. Springer Publishing Company, Incorporated.
- J. Rabaey, Chandrakasan, A,, Nikolic, B. 2004. Digital integrated circuits- A design perspective. Prentice Hall.
- A. Chandrakasan, W. Bowhill, and F. Fox. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press
- M. Alioto (ed), Enabling the Internet of Things: From Integrated Circuits to Integrated Systems, Springer 2017.
- Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA.
- Other References