Digital IC Design (August 2024): Difference between revisions

From Center for Integrated Circuits and Devices Research (CIDR)
Jump to navigation Jump to search
Line 14: Line 14:
! Module !! Date !! Topic !! Resources !! Activity
! Module !! Date !! Topic !! Resources !! Activity
|-
|-
| style="width: 5%"| 1 ||style="width: 20%"| 3 Sep 2024 ||style="width: 30%"| Introduction  
| style="width: 5%"| 1 ||style="width: 20%"| 10 Sep 2024 ||style="width: 30%"| Introduction  
|| [[video]]
|| [[video]]
|| [[Activity 1]]
|| [[Activity 1]]
|-
|-
| 2 || 10 Sep 2024 || MOS Transistor and Technology Scaling
| 2 || 17 Sep 2024 || MOS Transistor and Technology Scaling
|| [[video]]
|| [[video]]
|| [[Installing the Tools]]
|| [[Installing the Tools]]
|-
|-
| 3 || 17 Sep 2024 || CMOS Inverter and Delay models
| 3 || 24 Sep 2024 || CMOS Inverter and Delay models
|| [[ Inverter]]
|| [[ Inverter]]
|| [[Activity 3]]
|| [[Activity 3]]
|-
|-
| 4 || 24 Sep 2024 || CMOS Gates and Logical Effort
| 4 || 1 Oct 2024 || CMOS Gates and Logical Effort
|| [[ CMOS Gates]]
|| [[ CMOS Gates]]
[[Logical Effort]]
[[Logical Effort]]
|| [[CMOS Gates Exercise]]
|| [[CMOS Gates Exercise]]
|-
|-
| 5 || 1 Oct 2024 || Variability
| 5 || 8 Oct 2024 || Variability
|| [[video]]
|| [[video]]
|| [[Lab Exercise on Variability]]
|| [[Lab Exercise on Variability]]

Revision as of 19:34, 10 September 2024

  • First Semester AY 2024-2025
  • Course Credit: 4 units (3 units lecture, 1 unit lab)

Catalog Description

Fundamentals of MOSFETS. Technology and modelling. Scaling and limits of scaling. Design for deep-submicron CMOS – high speed. Design techniques for low power. Arithmetic circuits. Driving interconnect, high-speed signalling. Timing. Memory design. Design for testability.

Prerequisite: CoE 141 or equiv

Course Outline

Module Date Topic Resources Activity
1 10 Sep 2024 Introduction video Activity 1
2 17 Sep 2024 MOS Transistor and Technology Scaling video Installing the Tools
3 24 Sep 2024 CMOS Inverter and Delay models Inverter Activity 3
4 1 Oct 2024 CMOS Gates and Logical Effort CMOS Gates

Logical Effort

CMOS Gates Exercise
5 8 Oct 2024 Variability video Lab Exercise on Variability
Midterm Exam
6 Arithmetic Circuits video
7 Low power design techniques video
8 Timing video
9 Memory Design video Lab Exercise on Memory
10 Testing and Testability
11 Special Topics
Finals

References

  • review of semiconductor fundamentals [EEE 41]
  • review of transistors and transistor circuits [EEE 51]
  • Book References
    • J. Rabaey. 2009. Low Power Design Essentials. Springer Publishing Company, Incorporated.
    • J. Rabaey, Chandrakasan, A,, Nikolic, B. 2004. Digital integrated circuits- A design perspective. Prentice Hall.
    • A. Chandrakasan, W. Bowhill, and F. Fox. 2000. Design of High-Performance Microprocessor Circuits. Wiley-IEEE Press
    • M. Alioto (ed), Enabling the Internet of Things: From Integrated Circuits to Integrated Systems, Springer 2017.
    • Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective (4th. ed.). Addison-Wesley Publishing Company, USA.
  • Other References